数字验证工程师

地点：无锡

As a Digital Verification Engineer, your primary job function is to verify digital, memory-based and mixed/signal products. You will have the opportunity to be exposed and to work with a highly enthusiastic engineering team. 
Responsibilities 

• Understanding the expected functionality of designs 
• Working with designers on verification plan 
• Developing UVM verification environment 
• Running RTL and gate-level pre-simulation/regressions and post- simulations/regressions (direct cases and random cases) 
• Working with designers to analyze and debug the issue of design 
• Code/functional coverage development, analysis and closure 
• Creating scripts to improve the efficiency of verification 

Skills

• Familiar with System Verilog, UVM verification 
• Familiar with industry standard ASIC design and verification tools and flow 
• Exposure to Verilog/System Verilog language 
• Knowledge of scripting languages is a plus (Tcl, Perl, Phython) 
• Initiative, innovation, good communication and team player 
• Must have good problem-solving skills • Must be self-motivated Requirements 
• 3+ years of experience in verification environments, Bachelor or above of EE preferred 
• Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.) 
• Knowledge of Memory Chip/ Mixed signal verification is a plus